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[Other] arinc429_receiver

Description: Simple Arinc-429 receiver channel description on Verilog HDL with parameterized DATA and LABEL FIFOs.
Platform: | Size: 6144 | Author: scnn86 | Hits:

[Other] uart

Description: 该源码包是uart串口协议的verilog语言模型，主要包括了3个部分：波特率产生模块，uart接收模块，uart发送模块。(The source package is UART serial protocol Verilog language model, including 3 main parts: baud rate generation module, UART receiver module, UART transmission module.)
Platform: | Size: 2048 | Author: 叶古 | Hits:

[VHDL-FPGA-Verilog] parameter_uart_rx

Description: 串口接收模块，可以通过parameter，参数化配置传输速率、传输位宽和校验。采用Verilog语音编程实现。使用者根据串口的要求配置好参数，并根据缓冲的大小配置FIFO就可以使用。对帧错误（停止位不为高），检验错误和读FIFO超时（FIFO满的情况下，有新的数据到）等现象进行了检查。(UART serial receiver module, through parameter, configuration parameters of the transmission rate, Data width and parity. Using Verilog. The user configured the parameters according to the serial port and configured FIFO according to the size of the buffer. The frame error (stop bit is not high), check errors, and read FIFO timeout (when FIFO is full,and new data come) and so on are examined.)
Platform: | Size: 4096 | Author: 老工程师 | Hits:

[VHDL-FPGA-Verilog] Clock_Synchronization_Module

Description: 数字接收机中频部分数字时钟的设计 包括matlab仿真 verilog代码、 testbench代码 以及word设计文档(Design of medium frequency digital clock in digital receiver Including Matlab simulation Verilog, testbench code, and design documents)
Platform: | Size: 245760 | Author: nokkk | Hits:

[VHDL-FPGA-Verilog] FFT_Module

Description: 接收机数字部分FFT模块的代码 包括verilog代码、 matlab仿真、 word文档 testbench 实现FFT(The code of the digital part FFT module of the receiver Including Verilog, matlab simulation, testbench Implementation of FFT)
Platform: | Size: 6002688 | Author: nokkk | Hits:

[VHDL-FPGA-Verilog] Orthogonization_Module

Description: 接收机数字部分正交混频模块‘ 包括verilog代码 matlab仿真 word文档 testbench代码(Receiver digital part orthogonal frequency mixing module ' Including Verilog code Matlab simulation Testbench code)
Platform: | Size: 1798144 | Author: nokkk | Hits:

[VHDL-FPGA-Verilog] CIC_Filter_Module

Description: 数字接收机cic抽取模块 抽取倍数可以选择 包括verilog代码 word文档 matlab仿真 testbench代码(CIC decimation module of digital receiver Extraction multiple can be selected Including Verilog code Word document Matlab simulation Testbench code)
Platform: | Size: 3013632 | Author: nokkk | Hits:

[3G develop] 95b4abf558734ca9a899a0b792ce3f84

Description: OFDM的接收机代码，使用Verilog写的，搬运(Receiver code for OFDM)
Platform: | Size: 1496064 | Author: letiant | Hits:
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